
ADuC7060
TIMERS
The ADuC7060 features four general-purpose timer/counters.
Table 76. Timer Event Capture
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Timer0
Timer1 or wake-up timer
Timer2 or watchdog timer
Timer3
Bit
0
1
2
Description
Reserved
Timer0
Timer1 or wake-up timer
The four timers in their normal mode of operation can be either
free running or periodic.
In free running mode, the counter decrements/increments from
the maximum or minimum value until zero/full scale and starts
again at the maximum or minimum value.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero/full scale and
starts again at the value stored in the load register. Note that the
TxLD MMR should be configured before the TxCON MMR.
The value of a counter can be read at any time by accessing its
value register (TxVAL). Timers are started by writing in the
control register of the corresponding timer (TxCON).
In normal mode, an IRQ is generated each time the value of the
counter reaches zero (if counting down) or full scale (if
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Timer2 or watchdog timer
Timer3
Reserved
Reserved
Reserved
ADC
UART
SPI
XIRQ0
XIRQ1
I 2 C master
I 2 C slave
PWM
XIRQ2 (GPIO IRQ2)
XIRQ3 (GPIO IRQ3)
counting up). An IRQ can be cleared by writing any value to the
clear register of the particular timer (TxCLRI).
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